The invention relates to interfacing circuitry for converting linear logic signals such as ECL logic to digital logic such as TTL.
A common technique employed in large scale integrated (LSI) digital circuits to achieve maximum speed is to utilize linear circuit operation internally which is buffered at the inputs and outputs for digital compatability. The digital to linear operation at the input can readily be achieved by utilizing a common single ended differential amplifier. However, the linear to digital translation at the output is considerably more difficult because the linear logic levels are referenced to the positive supply while the digital logic levels are referenced to the negative supply or ground in the case of TTL type logic. Further, difficulty is encountered with power supply variations which have the effect of varying the linear logic levels and hence makes the linear to digital translation even more difficult. It would thus be advantageous to provide a linear to digital translator which can perform very fast linear to digital translation which is immune from power supply variations.
A translation arrangement which provides, independent of power supply variations, interfacing between a linear circuit and TTL logic senses the differential voltage in the linear circuit, which for the purposes of this discussion will be designated as ECL logic. By sensing the differential output voltage of the ECL circuit as compared to sensing only a comparatively large single ended voltage swing, the translator is made insensitive to variations in power supply voltage. Differential sensing of the input also provides the further advantage of excellent common mode rejection making the translator substantially immune to common mode noise signals from the ECL circuit stage.
A prior art ECL to TTL converter of the differential type is described in U.S. Pat. No. 4,045,690 issued to Tam on Aug. 30, 1977. The Tam converter or translator as it is sometimes termed is comprised of two parallel current paths terminating in a current mirror. A first current path includes resistor R.sub.1 and transistor Q.sub.3, with the other current path including resistor R.sub.2 and transistor Q.sub.4. The resistors are of equal value and transistors Q.sub.3 and Q.sub.4 are matched. These current paths connect to the current mirror comprised of transistors QD and Q.sub.2. While the Tam device was a step forward in the art of linear to digital translation, it exhibits several deficiencies. For example, the Tam device utilizes a saturating device (Q.sub.1) which because it saturates reduces the speed of translator operation. Further, Tam requires biasing of the translator output at the threshold of the TTL gate or buffer in order to achieve high speed operation. That is, the Tam TTL gate, which has a two diode voltage drop threshold level, is interfaced with the translator whose output is maintained at a two diode voltage drop. Switching of the TTL gate is effected by increasing or decreasing the two diode drop voltage output of the translator by .DELTA.V, the differential input voltage. Such a biasing arrangement can result in undesirable oscillation of the translator output as well as degradation of the TTL gate output. A still further drawback of the Tam device involves crossover performance whenever the differential voltage, .DELTA.V, changes. Crossover refers to the switching of the converter output and thus the state of the TTL buffer in response to a reversal of the input differential voltage. Proper crossover response assures that the buffer output transistors turn on in response to a logic low input from the ECL gate and turn off in response to a logic high input.
The present invention overcomes the various drawbacks of the Tam type differential ECL to TTL translator to produce a high speed linear to digital translation with improved crossover response and without TTL output degradation, while maintaining the advantages of differential linear digital translation exhibited by Tam.